Current inspection apparatus examine complete packaged devices. If many defective devices were found (poor yield case), many complete devices should be abandoned. Not only chips but also stems, caps, wirings and other elements which accompany packages shall be wasted. Labor of packaging and wirings shall be lost. Inspection in a state of wafers or a state of chips would be far favorable than the current inspection in a final state of complete, packaged devices for avoiding such a big loss. An as-wafer examination would be preferable to an as-chip examination from the standpoints of reducing time and cost. But the as-wafer examination is forbidden for optoelectronic devices which cause light/electricity conversion. Difficulty of treatment of light inhibits the as-wafer examination. In the case of light emitting devices of LEDs and LDs, the emission property is examined by supplying a current to an object device for producing light and detecting the light. In the case of light receiving (detecting) devices of PDs and APDs, the detection property is examined by irradiating an object device with a test beam which has been prepared by an outer light source and measuring a photocurrent induced by the light. Thus optoelectronic devices (photodevices) cannot be examined in the state of a wafer. The as-wafer examination is impossible for photodevices. Furthermore the inspection in the state of a chip is also inapplicable to photodevices. Then the as-wafer examination and the as-chip examination have been inapplicable to photodevices.
Current inspection methods examine emission/detection properties of completed devices which have stored and sealed chips in packages in a thermostat by changing surrounding temperatures from −40° C. to +85° C. As-package inspection is prevalent in photodevices at present. Problems accompany the as-package inspection. When a device is judged as a bad one, the device is abandoned as a whole. Packages and labor and time of packaging (welding, wiring) are wasted. Occurrence of big loss is undesirable. These are drawbacks of the current as-package inspection.
It would be the most favorable to judge whether chips are good or bad before being packaged to complete devices. It is named as-chip inspection here. It would alleviate package cost and packaging labor cost. At present no as-chip inspection method has been contrived. High temperature or room temperature characteristics would be able to be examined in a state of chips even at present by placing a chip on a stage kept at a high temperature (+85° C.) or room temperature (+25° C.), supplying a current/voltage to the chip and measuring emission/detection properties of the chip.
However, the as-chip inspection is impossible to apply to the low temperature inspection because low temperatures induce water vapor included in the atmospheric air to condense into water at a temperature as low as −40° C. Condensed water wets the chip, stage, probe and other elements. The examination is impossible. The chip is debased. Thus no as-chip examination is available for low temperatures at present.
Japanese Patent Laying Open No. 10-289934 proposed a probing apparatus and a probing method for examining low temperature characteristics of device units processed on a wide silicon wafer unit by unit by protecting the processed wafer from water condensation. The proposed probing apparatus includes a stage movable in X-, Y- and Z-directions, a probe for testing units, a probe chamber having the stage and the probe, a conveying apparatus with an arm, a loader chamber having the conveying apparatus and a partition wall having a hole and furnished between the probe chamber and the loader chamber. The apparatus tests device units made on a silicon wafer by holding the fabricated wafer on an arm of the conveying apparatus, extending the arm via the hole, placing the wafer on a stage of the probe chamber, pulling the arm back to the loader chamber, cooling the wafer/stage to −60° C., lifting the cooled stage/wafer, bringing the wafer into contact with a plurality of probes, supplying dry air having a dew point of −70° C., allotting currents to all the units via the probes and examining electronic properties of all the units at a stretch.
The arm of the conveying apparatus carries the examined cold wafer to the loader chamber. In the loader chamber the wafer is warmed by blowing hot air with a temperature of 80° C. The hot wafer is immune from being contaminated with water or particles. A contrivance is to heat the examined cool wafer by hot air in the loader chamber for avoiding contamination. The apparatus can examine plenty of electronic device (not photodevice) units fabricated upon a 12 inch (300 mm) diameter silicon (Si) wafer by many probes at a stretch. The apparatus has a big loader chamber and a wide probe chamber since the wide stage rises and sinks, and the conveying apparatus carries the large wafer by long arms. An inner space of the probe chamber is quite wide. The wide inner space requires a huge consumption of dry air.
This is a large-sized apparatus for judging whether electronic properties of plenty of electronic device units are good or bad by many probes at a stroke. However, the apparatus can measure only electronic properties which are detected by probes. Objects are transistors, field effect transistors (FETs), large scaled integration circuits (LSIs) and other exclusively-electronic devices. The apparatus cannot examine LEDs, LDs or PDs which require emission/detection measurements. Japanese Patent Laying Open No. 10-289934 is entirely inapplicable to low temperature photocharacteristic examination of photodevices. This is explained here due to the description of a low temperature examination.
Japanese Patent Laying Open No. 10-321683 proposed a probing apparatus and a method for examining electric properties of device units produced on a 300 mm diameter silicon wafer in a manner similar to the aforementioned Japanese Patent Laying Open No. 10-289934. The apparatus includes a probe chamber, a loader chamber and a conveying apparatus. Horizontally expanding/shrinking arms of the conveying apparatus carry a wafer between the probe chamber and the loader chamber. The stage (main chuck) in the probe chamber can cool the wafer down to a predetermined low temperature. The stage can ascend and descend. Receiving a wafer from the arm, the stage rises and brings device units of the wafer into contact with a plurality of probes furnished on an upper wall of the probe chamber. Japanese Patent Laying Open No. 10-321683 points out a serious problem. When the wafer is lifted up into contact with the probes, a space between the wafer and the probe chamber wall is so narrow that dry air cannot sufficiently pervade the nearly closed wafer/probe space. Insufficient supply of dry air fails to replace residual air in the probe/wafer space completely by dry air. The residual air is condensed to water by cooling. The water wets the wafer and the probes. This is the matter of Japanese Patent Laying Open No. 10-321683.
Japanese Patent Laying Open No. 10-321683 suggested a contrivance of introducing dry air into the probe/wafer space by piercing the space with a dry-air supplying pipe. Japanese Patent Laying Open No. 10-321683 also examines electronic properties of electronic devices in a state of a wafer. This tests electronic characteristics of devices fabricated on a 300 mm diameter silicon wafer. Japanese Patent Laying Open No. 10-321683 is inapplicable to photodevices. Japanese Patent Laying Open No. 10-321683 is entirely incompetent for the examination of LEDs, LDs, PDs and APDs. This is described here owing to the description of use of dry air.
Examination of light emitting devices, e.g., light emitting diodes (LEDs) and laser diodes (LDs) and light detection devices, e.g., photodiodes (PDs) and avalanche photodiodes (APDs) requires actual light production or light reception. Necessity of light exchange prevents people from examining light emitting or receiving devices in a state of as-wafer devices. The techniques proposed by Japanese Patent Laying Open No. 10-289934 and Japanese Patent Laying Open No. 10-321683 are inapplicable to the inspection of light emitting-/receiving devices. A fabricated wafer is cut into plenty of small units of devices by scribing and separating. A small unit is called a device “chip”. Furthermore current photodevice examining methods are inapplicable even to as-chip devices.
Current inspection methods for photodevices can examine neither as-chip devices nor as-wafer devices. At present, no photodevice inspection method can examine photodevices in a state as a chip. The current inspection methods can examine completely fabricated light emitting/detecting devices encapsulated into packages and equipped with lead pins. In the case of light emitting devices (LED and LD), the photocharacteristics are examined by carrying a packaged LED or LD onto a test socket, inserting lead pins into holes of the stage, supplying a driving current via the lead pins of the package, making the device to emit light via an upper window of the package and measuring the power and spectrum of via-window emitted light. In the case of light receiving devices (PD, APD and PTR), the photocharacteristics are examined by carrying a packaged PD, APD or PTR onto a test socket, inserting lead pins into holes of the stage, applying a reverse bias voltage via the lead pins of the package, irradiating the device by a test beam and measuring a photocurrent caused by the test beam. This method is called “as-package” inspection, from which the as-wafer or as-chip inspection is entirely different.
Drawbacks accompany the as-package inspection. When a complete device is judged as a reject, the whole must be abandoned. The package is also a waste.
Packaging task is lost in vain. A package contains leadpins, a disc stem, a lens, a windowed cap and inert gas. Packaging requires adhesion, wiring, alignment, gas-replacement and welding. The as-package inspection invites a great loss. If the yield, which is a ratio of good ones to the whole, is sufficiently high close to 100%, the loss is small. But the yield is not always high for the production of LDs, LEDs and PDs for optical communications.
A more desirable one is an inspection apparatus which would be able to inspect photochacteristics of device chips and would judge whether the chip is good or bad in the stage of a chip before being packaged. When a chip is judged as bad, wastage is only the chip. The pre-package examination can save a package and packaging cost for the inherently bad chip. Such an as-chip examination can reduce the cost caused by defective products to about ⅕ of the current packaged-device examination.
There is no inspection device capable of examining the properties of as-chip LED, LD or PD devices at present. If a chip were cooled down to a temperature as low as −40° C., water-vapor contained in the atmosphere would be condensed into water and the water would wet the chip, the probe pushing the chip and the stage holding the chip. Wetted probe, stage and device would be useless. Thus low-temperature inspection of as-chip devices would fail. An alternative would be the use of a thermostat. It may be probable to fetch a chip into a thermostat, cooling the inner space to a low temperature of e.g., −40° C., applying a current to the chip and measuring light power emitted from the chip. However, the test cycle of storing a chip into a large thermostat, cooling the thermostat, giving the chip a current and measuring photo-properties of the chip would consume a long time. It would raise cost far higher than the current as-package examination. Thus there is no as-chip examination apparatus for photodevices at present.